Copper is widely used as an interconnect material in Back-End-of-Line (BEOL) because it has high thermal conductivity and good electromigration failure resistance. However, RF applications require a larger number of ultra-thick copper metals combined with a high metal density. Due to high CTE mismatch of the copper interconnects to silicon a high wafer bow is induced during the BEOL process steps. A main contribution for the high wafer bow is the stress induced in the wafer due to annealing process steps at elevated temperature. The current study focuses on the effect of line width and annealing temperatures on stress relaxation and microstructural evolution due to aging for one month. In addition, the effect of microstructural change is studied with the time dependent wafer bow measurement showing stress relaxation over time.