We propose and demonstrate an efficient approach to extract key parameters of GaN-based 2DEG heterostructures grown on conducting Silicon substrates. The methodology enables an electrical feedback on different epitaxial design or MOCVD growth conditions in a very short-time frame by means of vertical capacitance-voltage (C-V) measurement on simple gate-metal top-electrodes, which are evaporated through a shadow mask. Key parameters such as sheet charge carrier density of the 2DEG-channel, (AlGaN) barrier thickness between 2DEG and top-electrode and threshold voltage of 2DEG depletion can be extracted with minimum effort. All respective parameters can be logged across the entire wafer without the need for a sophisticated device process and reveal the lateral (in-) homogeneity of the wafer material. In addition, this method can be used to mimic the gate-module of metal-insulator-semiconductor (MIS)-HEMTs and, therefore, to study different charge-related properties of the dielectric-GaN interface or the dielectric layer itself.