Improved high-temperature etch processing of high-k metal gate stacks in scaled TANOS memory devices

Research output: Contribution to journalResearch articleContributedpeer-review

Contributors

  • J. Paul - , Fraunhofer Institute for Electronic Nano Systems (Author)
  • V. Beyer - , Fraunhofer Institute for Electronic Nano Systems (Author)
  • M. Czernohorsky - , Fraunhofer Institute for Electronic Nano Systems (Author)
  • M. F. Beug - , National Metrology Institute of Germany (PTB) (Author)
  • K. Biedermann - , Fraunhofer Institute for Electronic Nano Systems (Author)
  • M. Mildner - , Fraunhofer Institute for Electronic Nano Systems (Author)
  • P. Michalowski - , Fraunhofer Institute for Electronic Nano Systems (Author)
  • E. Schütze - , Fraunhofer Institute for Electronic Nano Systems (Author)
  • T. Melde - , Fraunhofer Institute for Electronic Nano Systems (Author)
  • S. Wege - , Plasway-Technologies GmbH (Author)
  • R. Knöfler - , Infineon Technologies AG (Author)
  • T. Mikolajick - , Chair of Nanoelectronics, Freiberg University of Mining and Technology (Author)

Abstract

Reactive ion etching using BCl3-based plasma chemistries is a promising technique to pattern high-k metal gate stacks. High-k materials for non-volatile memory and CMOS applications, in particular Al2O3, possess high chemical resistance. Accordingly, a steep sidewall angle at the device edges is difficult to achieve by reactive ion etching. Advanced etch conditions at elevated temperatures (above 250 °C) is an alternative to solve this challenge but generate various other technological difficulties. In particular the patterning of TANOS devices reveals severe etch damage effects at the metal gate layer. A study of damage protection has been carried out and in particular the chemical stability of different metal gate options during plasma treatments was investigated in detail. Advanced process approaches to prevent the metal gate deterioration are proposed.

Details

Original languageEnglish
Pages (from-to)1629-1633
Number of pages5
JournalMicroelectronic Engineering
Volume87
Issue number5-8
Publication statusPublished - May 2010
Peer-reviewedYes

External IDs

ORCID /0000-0003-3814-0378/work/156338412

Keywords

Keywords

  • AlO, Damage, Decoupled plasma source, Dry etch, Encapsulation liner, High-k dielectric, High-temperature etch, Metal gate, TaN, TANOS