Compact model for the grounded-gate nMOS behaviour under CDM ESD stress

Research output: Contribution to journal › Conference article › Contributed › peer-review

Contributors

  • Christian Russ - , Interuniversitair Micro-Elektronica Centrum (Author)
  • Koen Verhaege - , Interuniversitair Micro-Elektronica Centrum (Author)
  • Karlheinz Bock - , Chair of Electronic Packaging Technology, Interuniversitair Micro-Elektronica Centrum (Author)
  • Philippe J. Roussel - , Interuniversitair Micro-Elektronica Centrum (Author)
  • Guido Groeseneken - , Interuniversitair Micro-Elektronica Centrum (Author)
  • Herman E. Maes - , Interuniversitair Micro-Elektronica Centrum (Author)

Abstract

The parasitic bipolar transistor inherent to grounded gate nMOS transistors is modelled, accounting for the specific conditions applied by CDM ESD stress. The avalanching, the triggering of snapback and the CDM-specific bipolar saturation mode are addressed. The optimal gate length for CDM protection in advanced submicron technologies is discussed.

Details

Original languageEnglish
Pages (from-to)302-315
Number of pages14
Journal Electrical Overstress Electrostatic Discharge Symposium proceedings
Publication statusPublished - 1996
Peer-reviewedYes

Conference

TitleProceedings of the 1996 Electrical Overstress/Electrostatic Discharge Symposium
Duration10 - 12 September 1996
CityOrlando, FL, USA

External IDs

ORCID /0000-0002-0757-3325/work/139064819

Keywords

ASJC Scopus subject areas