ZuSE-KI-Mobil: AI Chip Design Platform for Automotive and Industrial Applications

Research output: Contribution to journalResearch articleInvitedpeer-review

Contributors

  • Shaown Mojumder - , Vodafone Chair of Mobile Communications Systems (Author)
  • Simon Friedrich - , Vodafone Chair of Mobile Communications Systems (Author)
  • Emil Matus - , Vodafone Chair of Mobile Communications Systems (Author)
  • Matthias Luders - , Leibniz University Hannover (LUH) (Author)
  • Martin Friedrich - , Leibniz University Hannover (LUH) (Author)
  • Oliver Renke - , Leibniz University Hannover (LUH) (Author)
  • Holger Blume - , Leibniz University Hannover (LUH) (Author)
  • Markus Kock - , Dream Chip Technologies GmbH (Author)
  • Gregor Schewior - , Dream Chip Technologies GmbH (Author)
  • Darius Grantz - , Dream Chip Technologies GmbH (Author)
  • Jens Benndorf - , Dream Chip Technologies GmbH (Author)
  • Julian Hoefer - , Karlsruhe Institute of Technology (Author)
  • Patrick Schmidt - , Karlsruhe Institute of Technology (Author)
  • Jurgen Becker - , Karlsruhe Institute of Technology (Author)
  • Nael Fasfous - , BMW Group (Author)
  • Pierpaolo Mori - , BMW Group (Author)
  • Hans Jorg Vogel - , BMW Group (Author)
  • Samira Ahmadifarsani - , Technical University of Munich (Author)
  • Leonidas Kontopoulos - , Technical University of Munich (Author)
  • Ulf Schlichtmann - , Technical University of Munich (Author)
  • Yun Jin Li - , Infineon Technologies AG (Author)
  • Gerhard P. Fettweis - , Vodafone Chair of Mobile Communications Systems (Author)

Abstract

The ZuSE-KI-Mobil (ZuKIMo) research project presents a heterogeneous system-on-chip (SoC) designed for use in a variety of automotive and industrial edge applications. Implemented using GlobalFoundries (GF) 22-nm FD-SOI technology, the SoC features a modular architecture with a configurable, bit-serial, mixed-precision neural processing unit (NPU) core. This core can be adapted to different use cases, comes with a compact instruction set, and improves the performance of dilated convolutions. A hardware-accelerated, tunable image signal processor (ISP) hyperparameter pipeline reduces tuning time and increases detection confidence for AI tasks. The system also incorporates a selective, per-layer fault-tolerance mechanism and supports rapid prototyping via an Apache TVM-driven compiler flow and cycle-accurate simulation. The adaptable hardware generation process is designed with future chiplet-based scaling in mind, providing a flexible foundation for upcoming heterogeneous SoC designs.

Details

Original languageEnglish
Pages (from-to)2961-2974
Number of pages14
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume33
Issue number11
Publication statusPublished - Nov 2025
Peer-reviewedYes

External IDs

ORCID /0009-0007-8401-7852/work/211722634

Keywords

Research priority areas of TU Dresden

Keywords

  • AI accelerator, autonomous systems, compiler, edge computing, system-on-chip (SoC)