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Research Portal of the TU Dresden

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

ISSNs: 1063-8210, 1557-9999

IEEE, New York [u. a.]

Scopus rating (2023): CiteScore 6.4 SJR 0.937 SNIP 1.516

Journal

Titles	IEEE Transactions on Very Large Scale Integration (VLSI) Systems IEEE transactions on very large scale integration (VLSI) systems
ISSNs	1063-8210, 1557-9999
Publisher	IEEE, New York [u. a.]
ZDB-ID	1151835-2
ZDB-ID	2034318-8

Keywords

ASJC Scopus subject areas

Software
Hardware and Architecture
Electrical and Electronic Engineering

Library keywords

004 Computer science

Related content

Research output

A Single-Ended High-Voltage-Compliant 11-bit Current-Steering Digital-to-Analog Converter for Adaptive Noise Cancellation in Power over Data Line Networks

Burkhardt, F., Protze, F. & Ellinger, F., 24 Nov 2024, (E-pub ahead of print) In: IEEE transactions on very large scale integration (VLSI) systems.

Research output: Contribution to journal › Research article › Contributed › peer-review

Hardware Implementation of an OPC UA Server for Industrial Field Devices

Bauer, H., Höppner, S., Iatrou, C., Charania, Z., Hartmann, S., Rehman, S. U., Dixius, A., & 9 othersEllguth, G., Walter, D., Uhlig, J., Neumärker, F., Berthel, M., Stolba, M., Kelber, F., Urbas, L. & Mayr, C., 1 Nov 2021, In: IEEE transactions on very large scale integration (VLSI) systems. 29, 11, p. 1998-2002 5 p., 9569952.

Research output: Contribution to journal › Research article › Contributed › peer-review

A novel hybrid DRAM/STT-RAM last-level-cache architecture for performance, energy, and endurance enhancement

Hameed, F. & Castrillon, J., Oct 2019, In: IEEE transactions on very large scale integration (VLSI) systems. 27, 10, p. 2375-2386 12 p., 8734763.

Research output: Contribution to journal › Research article › Contributed › peer-review

Designing Efficient Circuits Based on Runtime-Reconfigurable Field-Effect Transistors

Rai, S., Trommer, J., Raitza, M., Mikolajick, T., Weber, W. M. & Kumar, A., Mar 2019, In: IEEE transactions on very large scale integration (VLSI) systems. 27, 3, p. 560-572 13 p., 3.

Research output: Contribution to journal › Research article › Contributed › peer-review

An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~ W/Channel in 65-nm CMOS

Do, A. T., Zeinolabedin, S. M. A., Jeon, D., Sylvester, D. & Kim, T. T., 2019, In: IEEE transactions on very large scale integration (VLSI) systems. 27, 1, p. 126-137 12 p.

Research output: Contribution to journal › Research article › Contributed › peer-review

View all research output (10)