Wire resistance impact and compensation methods in analog switching 1R memristive crossbar arrays
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
This paper discusses the integration of a highly scalable and interfacial switching, multi-bit Ti/Al2O3/NbOx/Ti bi-layer memristor stack in the 3 × 3 passive crossbar array. In conjunction with wire resistance, impact and methodologies are discussed to enhance voltage delivery for effective two-bit vector matrix multiplication. Finally, parameter tuning strategies for dynamic program and erase of the cells by pulsed VDD/2 and VDD/3 schemes to realize multi-bit vector matrix multiplication are presented.
Details
| Original language | English |
|---|---|
| Article number | 109381 |
| Number of pages | 6 |
| Journal | Solid-state electronics |
| Volume | 236 |
| Publication status | Published - Oct 2026 |
| Peer-reviewed | Yes |
External IDs
| ORCID | /0000-0001-7436-0103/work/216552748 |
|---|---|
| ORCID | /0000-0003-3814-0378/work/216556491 |
| ORCID | /0000-0003-3259-4571/work/216556631 |
Keywords
ASJC Scopus subject areas
Keywords
- 1R crossbar array, Analog switching, Dynamic measurements, Interfacial switching, Memristor, VMM, Wire resistance