Wafer warpage generated during the back-end-of-line semiconductor manufacturing is caused by high residual stresses induced in the wafer due to the mismatch of the coefficient of thermal expansion between various materials, such as metals and dielectrics, at high processing temperatures. The study emphasizes the critical role of accurate material data as an input parameter in the Finite Element Method model for precise warpage prediction. The lack of temperature-dependent material data such as Young's modulus, plasticity, and creep coefficients for copper is a significant challenge for reliable wafer warpage prediction. This study uses various temperaturedependent nanoindentation methods to characterize copper for the temperature range from room temperature to $400^{\circ} \mathrm{C}$. The study describes a Finite Element Method model to predict wafer warpage and propose guidelines for warpage reduction efforts, focusing on the influence of different metal line width configurations on stress induced in the wafer. With the availability of material data, the mechanical response of the metal layers is modeled using non-linear plasticity and timedependent creep behavior to simulate their deformation under thermal loads typically encountered during back-end-of-line wafer processing.