Surrogate-Based Modeling Techniques for Mapping Transistor Figures of Merit onto Compact Model Parameters

Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review

Contributors

  • Fabio A.Velarde Gonzalez - , Fraunhofer Institute for Integrated Circuits (Author)
  • Jose L. Chavez-Hurtado - , Instituto Tecnológico y de Estudios Superiores de Occidente (Author)
  • Andre Lange - , Fraunhofer Institute for Integrated Circuits (Author)
  • Thomas Mikolajick - , Chair of Nanoelectronics, TUD Dresden University of Technology (Author)

Abstract

The electrical characteristics of a transistor can deviate from its nominal behavior due to process variations, aging mechanisms, etc. In order to ensure the reliability of a design, circuit level simulations capturing this altered transistor behaviors have become increasingly important. In this paper we study the use of surrogate models to map changes in key transistor's figures of merit into compact model parameters in order to shorten the path from reliability measurements to simulations.

Details

Original languageEnglish
Title of host publication2022 IEEE International Integrated Reliability Workshop (IIRW)
Number of pages5
ISBN (electronic)978-1-6654-5368-4
Publication statusPublished - 2022
Peer-reviewedYes

Publication series

SeriesIEEE International Integrated Reliability Workshop (IIRW)
ISSN1930-8841

Workshop

Title2022 IEEE International Integrated Reliability Workshop
SubtitleReliable electronics for a reliable society
Abbreviated titleIIRW 2022
Duration9 - 13 October 2022
LocationStanford Sierra Conference Center
CityFallen Leaf Lake
CountryUnited States of America

External IDs

ORCID /0000-0003-3814-0378/work/142256364

Keywords

ASJC Scopus subject areas

Keywords

  • BSIM, Compact Model, GRNN, HCI, Kriging, PSM, RSM, Surrogate models, SVM, Transistor aging