Speeding-Up Emerging Device Development Cycles by Generating Models via Machine-Learning directly from Electrical Measurements
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
In this work we present how an empirical compact model can be constructed directly from current measurement data by employing a machine learning technique. We demonstrate our approach on emerging dual-gated reconfigurable device test structures, which have been fabricated directly on an industrial 22 nm process. Variability of key figures of merit in reconfigurable field effect transistor test structures in the early development stage is analysed. The resulting model enables a fast adaptation to new geometries and provides simulation speed and convergence properties of a compact model, while being also flexibly adaptable to new technological iterations, thus speeding-up development cycles.
Details
| Original language | English |
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| Title of host publication | ESSERC 2024 - Proceedings |
| Publisher | IEEE Computer Society |
| Pages | 217-220 |
| Number of pages | 4 |
| ISBN (electronic) | 9798350388138 |
| Publication status | Published - 2024 |
| Peer-reviewed | Yes |
Publication series
| Series | European Conference on Solid-State Circuits (ESSCIRC) |
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| ISSN | 1930-8833 |
Conference
| Title | 50th IEEE European Solid-State Electronics Research Conference |
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| Subtitle | The Next Circuits for a Better Life |
| Abbreviated title | ESSERC 2024 |
| Conference number | 50 |
| Duration | 9 - 12 September 2024 |
| Website | |
| Location | Bruges Meeting & Convention Centre (BMCC) |
| City | Bruges |
| Country | Belgium |
External IDs
| ORCID | /0000-0003-3814-0378/work/180371979 |
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Keywords
ASJC Scopus subject areas
Keywords
- Compact Modelling, Emerging Devices, Fully-Depleted-Silicon-on-Insulator (FD-SOI), Machine Learning