Speeding-Up Emerging Device Development Cycles by Generating Models via Machine-Learning directly from Electrical Measurements

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • J. Trommer - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • M. Reuter - , Technische Universität Darmstadt (Author)
  • N. Bhattacharjee - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Y. He - , NaMLab - Nanoelectronic materials laboratory gGmbH, TUD Dresden University of Technology (Author)
  • V. Sessi - , Global Foundries Dresden (Author)
  • M. Drescher - , Global Foundries Dresden (Author)
  • M. Zier - , Global Foundries Dresden (Author)
  • M. Simon - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • K. Ruttloff - , Global Foundries Dresden (Author)
  • K. Li - , Global Foundries Dresden (Author)
  • A. Zeun - , Global Foundries Dresden (Author)
  • A. S. Seidel - , Global Foundries Dresden (Author)
  • C. Metze - , Global Foundries Dresden (Author)
  • M. Grothe - , Global Foundries Dresden (Author)
  • S. Jansen - , Global Foundries Dresden (Author)
  • G. Galderisi - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • V. Havel - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • S. Slesazeck - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • J. Hoentschel - , Global Foundries Dresden (Author)
  • K. Hofmann - , Technische Universität Darmstadt (Author)
  • T. Mikolajick - , Chair of Nanoelectronics, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)

Abstract

In this work we present how an empirical compact model can be constructed directly from current measurement data by employing a machine learning technique. We demonstrate our approach on emerging dual-gated reconfigurable device test structures, which have been fabricated directly on an industrial 22 nm process. Variability of key figures of merit in reconfigurable field effect transistor test structures in the early development stage is analysed. The resulting model enables a fast adaptation to new geometries and provides simulation speed and convergence properties of a compact model, while being also flexibly adaptable to new technological iterations, thus speeding-up development cycles.

Details

Original languageEnglish
Title of host publicationESSERC 2024 - Proceedings
PublisherIEEE Computer Society
Pages217-220
Number of pages4
ISBN (electronic)9798350388138
Publication statusPublished - 2024
Peer-reviewedYes

Publication series

SeriesEuropean Conference on Solid-State Circuits (ESSCIRC)
ISSN1930-8833

Conference

Title50th IEEE European Solid-State Electronics Research Conference
SubtitleThe Next Circuits for a Better Life
Abbreviated titleESSERC 2024
Conference number50
Duration9 - 12 September 2024
Website
LocationBruges Meeting & Convention Centre (BMCC)
CityBruges
CountryBelgium

External IDs

ORCID /0000-0003-3814-0378/work/180371979

Keywords

Keywords

  • Compact Modelling, Emerging Devices, Fully-Depleted-Silicon-on-Insulator (FD-SOI), Machine Learning