Speeding-Up Emerging Device Development Cycles by Generating Models via Machine-Learning directly from Electrical Measurements
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
In this work we present how an empirical compact model can be constructed directly from current measurement data by employing a machine learning technique. We demonstrate our approach on emerging dual-gated reconfigurable device test structures, which have been fabricated directly on an industrial 22 nm process. Variability of key figures of merit in reconfigurable field effect transistor test structures in the early development stage is analysed. The resulting model enables a fast adaptation to new geometries and provides simulation speed and convergence properties of a compact model, while being also flexibly adaptable to new technological iterations, thus speeding-up development cycles.
Details
| Originalsprache | Englisch |
|---|---|
| Titel | ESSERC 2024 - Proceedings |
| Herausgeber (Verlag) | IEEE Computer Society |
| Seiten | 217-220 |
| Seitenumfang | 4 |
| ISBN (elektronisch) | 9798350388138 |
| Publikationsstatus | Veröffentlicht - 2024 |
| Peer-Review-Status | Ja |
Publikationsreihe
| Reihe | European Conference on Solid-State Circuits (ESSCIRC) |
|---|---|
| ISSN | 1930-8833 |
Konferenz
| Titel | 50th IEEE European Solid-State Electronics Research Conference |
|---|---|
| Untertitel | The Next Circuits for a Better Life |
| Kurztitel | ESSERC 2024 |
| Veranstaltungsnummer | 50 |
| Dauer | 9 - 12 September 2024 |
| Webseite | |
| Ort | Bruges Meeting & Convention Centre (BMCC) |
| Stadt | Bruges |
| Land | Belgien |
Externe IDs
| ORCID | /0000-0003-3814-0378/work/180371979 |
|---|
Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- Compact Modelling, Emerging Devices, Fully-Depleted-Silicon-on-Insulator (FD-SOI), Machine Learning