Speeding-Up Emerging Device Development Cycles by Generating Models via Machine-Learning directly from Electrical Measurements

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • J. Trommer - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • M. Reuter - , Technische Universität Darmstadt (Autor:in)
  • N. Bhattacharjee - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • Y. He - , NaMLab - Nanoelectronic materials laboratory gGmbH, Technische Universität Dresden (Autor:in)
  • V. Sessi - , Global Foundries Dresden (Autor:in)
  • M. Drescher - , Global Foundries Dresden (Autor:in)
  • M. Zier - , Global Foundries Dresden (Autor:in)
  • M. Simon - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • K. Ruttloff - , Global Foundries Dresden (Autor:in)
  • K. Li - , Global Foundries Dresden (Autor:in)
  • A. Zeun - , Global Foundries Dresden (Autor:in)
  • A. S. Seidel - , Global Foundries Dresden (Autor:in)
  • C. Metze - , Global Foundries Dresden (Autor:in)
  • M. Grothe - , Global Foundries Dresden (Autor:in)
  • S. Jansen - , Global Foundries Dresden (Autor:in)
  • G. Galderisi - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • V. Havel - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • S. Slesazeck - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • J. Hoentschel - , Global Foundries Dresden (Autor:in)
  • K. Hofmann - , Technische Universität Darmstadt (Autor:in)
  • T. Mikolajick - , Professur für Nanoelektronik, NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)

Abstract

In this work we present how an empirical compact model can be constructed directly from current measurement data by employing a machine learning technique. We demonstrate our approach on emerging dual-gated reconfigurable device test structures, which have been fabricated directly on an industrial 22 nm process. Variability of key figures of merit in reconfigurable field effect transistor test structures in the early development stage is analysed. The resulting model enables a fast adaptation to new geometries and provides simulation speed and convergence properties of a compact model, while being also flexibly adaptable to new technological iterations, thus speeding-up development cycles.

Details

OriginalspracheEnglisch
TitelESSERC 2024 - Proceedings
Herausgeber (Verlag)IEEE Computer Society
Seiten217-220
Seitenumfang4
ISBN (elektronisch)9798350388138
PublikationsstatusVeröffentlicht - 2024
Peer-Review-StatusJa

Publikationsreihe

ReiheEuropean Conference on Solid-State Circuits (ESSCIRC)
ISSN1930-8833

Konferenz

Titel50th IEEE European Solid-State Electronics Research Conference
UntertitelThe Next Circuits for a Better Life
KurztitelESSERC 2024
Veranstaltungsnummer50
Dauer9 - 12 September 2024
Webseite
OrtBruges Meeting & Convention Centre (BMCC)
StadtBruges
LandBelgien

Externe IDs

ORCID /0000-0003-3814-0378/work/180371979

Schlagworte

Schlagwörter

  • Compact Modelling, Emerging Devices, Fully-Depleted-Silicon-on-Insulator (FD-SOI), Machine Learning