Special Session: Mitigating Side-Channel Attacks Through Circuit to Application Layer Approaches

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Contributors

  • Nima Kavand - , TUD Dresden University of Technology (Author)
  • Armin Darjani - , Chair of Processor Design (Faculty of Computer Science), TUD Dresden University of Technology (Author)
  • Jens Trommer - , Faculty of Electrical and Computer Engineering, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Giulio Galderisi - , Chair of Nanoelectronics, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Thomas Mikolajick - , Chair of Nanoelectronics, TUD Dresden University of Technology, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Nicolai Muller - , Ruhr University Bochum (Author)
  • Amir Moradi - , Ruhr University Bochum (Author)
  • Chongzhou Fang - , University of California at Davis (Author)
  • Ning Miao - , University of California at Davis (Author)
  • Han Wang - , Temple University (Author)
  • P. D. Sai Manoj - , George Mason University (Author)
  • Houman Homayoun - , University of California at Davis (Author)
  • Benjamin Hettwer - , Robert Bosch GmbH (Author)
  • Luca Parrini - , Robert Bosch GmbH (Author)
  • Akash Kumar - , Chair of Processor Design (Faculty of Computer Science), TUD Dresden University of Technology (Author)

Abstract

Side-Channel Attacks (SCAs), which are always considered a severe threat to the security of the cryptographic circuits, today can also be employed to extract IP secrets and neural network models. Hence, developing novel security solutions at different design levels is crucial. In this paper, we explore recent countermeasures at the circuit, algorithmic, and microarchitecture levels. First, we explain how Reconfigurable Field-Effect Transistor (RFET), as a beyond CMOS technology, enables us to provide both IP and data protection against SCAs at the circuit level. Second, we investigate an automated method for generating masked circuits as an algorithmic solution, and then we review machine learning-based SCA detection mechanisms at the microarchitecture level. Finally, we discuss emerging threats of SCAs from the industrial point of view.

Details

Original languageEnglish
Title of host publicationProceedings - 2023 International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages8-17
Number of pages10
ISBN (electronic)9798400702891
Publication statusPublished - 2023
Peer-reviewedYes

Publication series

SeriesInternational Conference on Hardware/Software Codesign and System Synthesis (CODES)

Conference

Title2023 ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis
Abbreviated titleCODES+ISSS 2023
Duration17 - 22 September 2023
Website
Degree of recognitionInternational event
CityHamburg
CountryGermany

External IDs

ORCID /0000-0003-3814-0378/work/150330862

Keywords

Keywords

  • Emerging technology, Hardware security, Masking, Side-channel analysis