Simulation study for the CDM ESD behaviour of the grounded-gate NMOS

Research output: Contribution to journal › Research article › Contributed › peer-review

Contributors

  • C. Russ - , Interuniversitair Micro-Elektronica Centrum (Author)
  • K. Verhaege - , Interuniversitair Micro-Elektronica Centrum, Sarnoff Corporation (Author)
  • K. Bock - , Interuniversitair Micro-Elektronica Centrum (Author)
  • G. Groeseneken - , Interuniversitair Micro-Elektronica Centrum (Author)
  • H. E. Maes - , Interuniversitair Micro-Elektronica Centrum (Author)

Abstract

The parasitic bipolar transistor inherent to grounded gate nMOSts is modelled accounting for the specific conditions applied by CDM ESD stress. The impact of the gate length on the CDM-specific bipolar saturation mode is addressed. The different operation modes occurring during CDM ESD stress translate to self-heating which explains the observed test results.

Details

Original languageEnglish
Pages (from-to)1739-1742
Number of pages4
JournalMicroelectronics Reliability
Volume36
Issue number11-12
Publication statusPublished - 1996
Peer-reviewedYes
Externally publishedYes

External IDs

ORCID /0000-0002-0757-3325/work/139064988

Keywords

ASJC Scopus subject areas

Library keywords