Non-Volatile Inverter With 3D Cylindrical Metal-Ferroelectric-Metal Capacitor Realizing Digitized Voltage Output for Computing-In-Memory

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • K. Ota - , Sony Group Corporation (Author)
  • J. Okuno - , Sony Group Corporation (Author)
  • T. Yonai - , Sony Group Corporation (Author)
  • R. Ono - , Sony Group Corporation (Author)
  • Y. Shuto - , Sony Group Corporation (Author)
  • M. Sakakibara - , Sony Group Corporation (Author)
  • A. Kato - , Sony Group Corporation (Author)
  • Y. Ueno - , Sony Group Corporation (Author)
  • M. Lederer - , Fraunhofer Institute for Photonic Microsystems (Author)
  • P. Reinig - , Fraunhofer Institute for Photonic Microsystems (Author)
  • K. Seidel - , Fraunhofer Institute for Photonic Microsystems (Author)
  • R. Alcala - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • U. Schroeder - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • T. Mikolajick - , Chair of Nanoelectronics, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)

Abstract

A non-volatile Hf0.5Zr0.5O2(HZO)-based Metal-Ferroelectric-Metal (MFM) inverter enabling AND/XNOR operations for Computation-in-Memory CiM) is proposed. Owing to the symmetric threshold voltage Vth) shift in the nFET and pFET of the MFM inverter, a digitized output after the multiply operation is successfully demonstrated for the first time with non-volatile memory, enabling the high precision CiM. In addition, the MFM inverter has the advantage of a large memory window (MW) because a large partial programming voltage is structurally applied to the MFM capacitor. Moreover, the MW and the endurance were intensively studied to clarify the key factors for reliable operation. Together with the process compatible FeRAM as a working memory, the MFM inverter has the potential to achieve low-power, high-density, and high precision non-volatile CiM systems.

Details

Original languageEnglish
Title of host publicationProceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
PublisherIEEE Computer Society
Pages61-64
Number of pages4
ISBN (electronic)979-8-3315-2539-2, 979-8-3315-2538-5
ISBN (print)979-8-3315-2540-8
Publication statusPublished - 2025
Peer-reviewedYes

Publication series

SeriesEuropean Solid-State Circuits Conference
ISSN1930-8833

Conference

Title51st IEEE European Solid-State Electronics Research Conference
Abbreviated titleESSERC 2025
Conference number51
Duration8 - 11 September 2025
Website
LocationTechnische Universität München
CityMünchen
CountryGermany

External IDs

ORCID /0000-0003-3814-0378/work/202352139

Keywords

Keywords

  • Computing in Memory, Ferroelectric, HfZrO