Non-Volatile Inverter With 3D Cylindrical Metal-Ferroelectric-Metal Capacitor Realizing Digitized Voltage Output for Computing-In-Memory

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • K. Ota - , Sony Group Corporation (Autor:in)
  • J. Okuno - , Sony Group Corporation (Autor:in)
  • T. Yonai - , Sony Group Corporation (Autor:in)
  • R. Ono - , Sony Group Corporation (Autor:in)
  • Y. Shuto - , Sony Group Corporation (Autor:in)
  • M. Sakakibara - , Sony Group Corporation (Autor:in)
  • A. Kato - , Sony Group Corporation (Autor:in)
  • Y. Ueno - , Sony Group Corporation (Autor:in)
  • M. Lederer - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • P. Reinig - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • K. Seidel - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • R. Alcala - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • U. Schroeder - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • T. Mikolajick - , Professur für Nanoelektronik, NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)

Abstract

A non-volatile Hf0.5Zr0.5O2(HZO)-based Metal-Ferroelectric-Metal (MFM) inverter enabling AND/XNOR operations for Computation-in-Memory CiM) is proposed. Owing to the symmetric threshold voltage Vth) shift in the nFET and pFET of the MFM inverter, a digitized output after the multiply operation is successfully demonstrated for the first time with non-volatile memory, enabling the high precision CiM. In addition, the MFM inverter has the advantage of a large memory window (MW) because a large partial programming voltage is structurally applied to the MFM capacitor. Moreover, the MW and the endurance were intensively studied to clarify the key factors for reliable operation. Together with the process compatible FeRAM as a working memory, the MFM inverter has the potential to achieve low-power, high-density, and high precision non-volatile CiM systems.

Details

OriginalspracheEnglisch
TitelProceedings - 51st IEEE European Solid-State Electronics Research Conference, ESSERC 2025
Herausgeber (Verlag)IEEE Computer Society
Seiten61-64
Seitenumfang4
ISBN (elektronisch)979-8-3315-2539-2, 979-8-3315-2538-5
ISBN (Print)979-8-3315-2540-8
PublikationsstatusVeröffentlicht - 2025
Peer-Review-StatusJa

Publikationsreihe

ReiheEuropean Solid-State Circuits Conference
ISSN1930-8833

Konferenz

Titel51st IEEE European Solid-State Electronics Research Conference
KurztitelESSERC 2025
Veranstaltungsnummer51
Dauer8 - 11 September 2025
Webseite
OrtTechnische Universität München
StadtMünchen
LandDeutschland

Externe IDs

ORCID /0000-0003-3814-0378/work/202352139

Schlagworte

Schlagwörter

  • Computing in Memory, Ferroelectric, HfZrO