Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
This paper presents the set of simulation means used to develop the concept of N2C2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation, compact modeling and EM simulation are leveraged through a Design-Technology Co-Optimization (DTCO) to achieve innovative 3D circuit architectures. Further, System-Technology Co-Optimization (STCO) implications on 3D NN system architecture are explored.
Details
| Original language | English |
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| Title of host publication | 2021 IEEE International Electron Devices Meeting, IEDM 2021 |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Chapter | 15.6.1-15.6.4 |
| ISBN (electronic) | 9781665425728 |
| Publication status | Published - 2021 |
| Peer-reviewed | Yes |
Publication series
| Series | Technical Digest / International Electron Devices Meeting (IEDM) |
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| Volume | 2021-December |
| ISSN | 0163-1918 |
Conference
| Title | 2021 IEEE International Electron Devices Meeting |
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| Subtitle | Devices for a New Era of Electronics: From 2D Materials to 3D Architectures |
| Abbreviated title | IEDM 2021 |
| Conference number | 67 |
| Duration | 11 - 16 December 2021 |
| Location | Hilton San Francisco Union Square Hotel & online |
| City | San Francisco |
| Country | United States of America |
External IDs
| ORCID | /0000-0003-3814-0378/work/142256165 |
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