Localized charge trapping memory cells in a 63 nm generation with nanoscale epitaxial cobalt salicide buried bitlines
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
A 63nm Twin Flash memory cell with a size of 0.0225μm2 per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi2 process allows the salicidation of local buried bitlines with only a few tens of nanometer width.
Details
| Original language | English |
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| Title of host publication | 2007 MRS Spring Meeting |
| Publisher | Materials Research Society |
| Pages | 65-70 |
| Number of pages | 6 |
| ISBN (print) | 9781558999572 |
| Publication status | Published - 2007 |
| Peer-reviewed | Yes |
| Externally published | Yes |
Publication series
| Series | Materials Research Society Symposium Proceedings |
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| Volume | 997 |
| ISSN | 0272-9172 |
Conference
| Title | 2007 MRS Spring Meeting |
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| Duration | 10 - 13 April 2007 |
| City | San Francisco, CA |
| Country | United States of America |
External IDs
| ORCID | /0000-0003-3814-0378/work/156338396 |
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