A 63nm Twin Flash memory cell with a size of 0.0225μm² per 2 (or 4) bits is presented. To achieve small cell areas, a buried bit line and an aggressive gate length of 100 nm are the key features of this cell together with a minimum thermal budget processing. A novel epitaxial CoSi₂ process allows the salicidation of local buried bitlines with only a few tens of nanometer width.