Given the increasing demand for highly integrated, high-performance packaging, this paper investigates packaging technologies for embedding chips and antennas in highfrequency applications. We propose a fan-out wafer-level packaging (FOWLP) approach that utilizes a semi-additive redistribution layer (RDL) to route high-frequency signals from embedded dies to an antenna array board. Copper (Cu) pillars act as lowloss interconnects between the RDL and the antenna substrate. To enable efficient signal transfer and minimize insertion loss, the semi-additive process is optimized to fabricate RDLs directly on embedded chips within an epoxy molding compound (EMC). The performance of these high-speed interconnects is evaluated through both simulation and S-parameter measurements. The signal path in the design includes grounded coplanar waveguides (GCPW) on the chips, coplanar waveguides (CPW) connecting the two chips, and their associated interfaces. The de-embedded insertion loss of the CWP connecting the 6 mm edge-to-edge chips at 180 GHz is approximately 10 dB, corresponding to a normalized loss below 1.9dB/mm. This result aligns well with simulations and is comparable to state-of-the-art technologies. Overall, this embedding-first approach effectively minimizes parasitic effects in chip-to-chip and chip-to-antenna connections. The techniques presented here could support the development of high-density, multi-layer RDLs with fine pitch and low parasitic loss, tailored for millimeter-wave (mmWave) applications.