Influence of gate length on ESD-performance for deep submicron CMOS technology

Research output: Contribution to journal › Research article › Contributed › peer-review

Contributors

  • K. Bock - , Interuniversitair Micro-Elektronica Centrum (Author)
  • B. Keppens - , Interuniversitair Micro-Elektronica Centrum (Author)
  • V. De Heyn - , Interuniversitair Micro-Elektronica Centrum (Author)
  • G. Groeseneken - , Interuniversitair Micro-Elektronica Centrum (Author)
  • L. Y. Ching - , National Semiconductor Corporation (Author)
  • A. Naem - , National Semiconductor Corporation (Author)

Abstract

The electrostatic discharge (ESD)-performance of grounded-gate nMOS protection structures is analyzed for a standard 0.25 μm CMOS epitaxial layer based technology. The shortest gate lengths show unexpectedly lower ESD-thresholds. This leads to an optimum performance for longer gate length devices attributed to the trade off between power dissipation and melt volume of the parasitic bipolar.

Details

Original languageEnglish
Pages (from-to)375-383
Number of pages9
JournalMicroelectronics Reliability
Volume41
Issue number3
Publication statusPublished - Mar 2001
Peer-reviewedYes
Externally publishedYes

External IDs

ORCID /0000-0002-0757-3325/work/139064979

Keywords

ASJC Scopus subject areas

Library keywords