Hot carrier degradation modeling of short-channel n-FinFETs suitable for circuit simulators
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
The hot-carrier (HC) degradation of short-channel n-FinFETs is investigated. The experiments indicate that interface trap generation over the entire channel length, which is enhanced near the drain region, is the main degradation mechanism. The relation of the hot-carrier degradation with stress time, channel length, fin width and bias stress voltages at the drain and gate electrodes is presented. A HC degradation compact model is proposed, which is experimentally verified. The good accuracy of the degradation model makes it suitable for implementation in circuit simulation tools. The impact of the hot-carriers on a CMOS inverter is simulated using HSPICE.
Details
Original language | English |
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Pages (from-to) | 10-16 |
Number of pages | 7 |
Journal | Microelectronics Reliability |
Volume | 56 |
Publication status | Published - 1 Jan 2016 |
Peer-reviewed | Yes |
Keywords
ASJC Scopus subject areas
Keywords
- Circuit aging, Degradation model, FinFET, Hot-carriers