Highly scalable 90nm STI bounded Twin Flash™ cell with local interconnect
Research output: Contribution to journal › Conference article › Contributed › peer-review
Contributors
Abstract
A 90nm Twin Flash memory cell with a size of 0.029μm2/bit (3.5F2) is presented. This cell is introduced first in a 1.8V, 2Gbit Data Flash. The Twin Flash technology is based on a shallow trench isolation (STI) bounded cell with local interconnect (LI) and serves for both advanced code and data flash storage memories. Beyond the 90nm node the scalability of the Twin Flash device is shown for 70 and 60nm node. The 90nm technology and its scaling follow the DRAM scaling path.
Details
| Original language | English |
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| Article number | 1469236 |
| Pages (from-to) | 120-121 |
| Number of pages | 2 |
| Journal | Digest of Technical Papers - Symposium on VLSI Technology |
| Volume | 2005 |
| Publication status | Published - 2005 |
| Peer-reviewed | Yes |
| Externally published | Yes |
Conference
| Title | 2005 Symposium on VLSI Technology |
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| Duration | 14 June 2005 |
| City | Kyoto |
| Country | Japan |
External IDs
| ORCID | /0000-0003-3814-0378/work/156338385 |
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