Highly scalable 90nm STI bounded Twin Flash™ cell with local interconnect

Publikation: Beitrag in FachzeitschriftKonferenzartikelBeigetragenBegutachtung

Beitragende

  • N. Nagel - , Infineon Technologies AG (Autor:in)
  • D. Olligs - , Infineon Technologies AG (Autor:in)
  • V. Polei - , Infineon Technologies AG (Autor:in)
  • S. Parascandola - , Infineon Technologies AG (Autor:in)
  • H. Boubekeur - , Infineon Technologies AG (Autor:in)
  • L. Bach - , Infineon Technologies AG (Autor:in)
  • T. Müller - , Infineon Technologies AG (Autor:in)
  • M. Strassburg - , Infineon Technologies AG (Autor:in)
  • S. Riedel - , Infineon Technologies AG (Autor:in)
  • P. Kratzert - , Infineon Technologies AG (Autor:in)
  • D. Caspary - , Infineon Technologies AG (Autor:in)
  • J. Deppe - , Infineon Technologies AG (Autor:in)
  • J. Willer - , Infineon Technologies AG (Autor:in)
  • N. Schulze - , Infineon Technologies AG (Autor:in)
  • T. Mikolajick - , Infineon Technologies AG (Autor:in)
  • K. H. Küsters - , Infineon Technologies AG (Autor:in)
  • A. Shappir - , Saifun Semiconductors Ltd. (Autor:in)
  • E. Redmard - , Saifun Semiconductors Ltd. (Autor:in)
  • I. Bloom - , Saifun Semiconductors Ltd. (Autor:in)
  • B. Eitan - , Saifun Semiconductors Ltd. (Autor:in)

Abstract

A 90nm Twin Flash memory cell with a size of 0.029μm2/bit (3.5F2) is presented. This cell is introduced first in a 1.8V, 2Gbit Data Flash. The Twin Flash technology is based on a shallow trench isolation (STI) bounded cell with local interconnect (LI) and serves for both advanced code and data flash storage memories. Beyond the 90nm node the scalability of the Twin Flash device is shown for 70 and 60nm node. The 90nm technology and its scaling follow the DRAM scaling path.

Details

OriginalspracheEnglisch
Aufsatznummer1469236
Seiten (von - bis)120-121
Seitenumfang2
FachzeitschriftDigest of Technical Papers - Symposium on VLSI Technology
Jahrgang2005
PublikationsstatusVeröffentlicht - 2005
Peer-Review-StatusJa
Extern publiziertJa

Konferenz

Titel2005 Symposium on VLSI Technology
Dauer14 Juni 2005
StadtKyoto
LandJapan

Externe IDs

ORCID /0000-0003-3814-0378/work/156338385

Schlagworte

ASJC Scopus Sachgebiete