High-endurance and low-voltage operation of 1T1C FeRAM arrays for nonvolatile memory application

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • Jun Okuno - , Sony Group Corporation (Author)
  • Takafumi Kunihiro - , Sony Group Corporation (Author)
  • Kenta Konishi - , Sony Group Corporation (Author)
  • Hideki Maemura - , Sony Group Corporation (Author)
  • Yusuke Shuto - , Sony Group Corporation (Author)
  • Fumitaka Sugaya - , Sony Group Corporation (Author)
  • Monica Materano - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Tarek Ali - , Fraunhofer Institute for Photonic Microsystems (Author)
  • Maximilian Lederer - , Fraunhofer Institute for Photonic Microsystems (Author)
  • Kati Kuehnel - , Fraunhofer Institute for Photonic Microsystems (Author)
  • Konrad Seidel - , Fraunhofer Institute for Photonic Microsystems (Author)
  • Uwe Schroeder - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Thomas Mikolajick - , Chair of Nanoelectronics, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Masanori Tsukamoto - , Sony Group Corporation (Author)
  • Taku Umebayashi - , Sony Group Corporation (Author)

Abstract

A novel 64 kbit one-transistor one-capacitor (1T1C) ferroelectric random access memory (FeRAM) array based on ferroelectric Hf0.5Zr0.5O2 (HZO) was proposed in a prior report. However, this array requires a low operation voltage for integration into advanced technology nodes, and its practical endurance remains unclear. To address these limitations, this study experimentally demonstrates the improved characteristics of a ferroelectric HfO2-based 1T1C FeRAM array. Thickness scaling of the ferroelectric HZO contributes to low-voltage operation of 1T1C FeRAMs, yielding 100% bit functionality at an operation voltage of 2.0 V and operating speed of 16 ns. Furthermore, the endurance performance of the 1T1C FeRAM memory array was investigated for the first time. Excellent cycling endurance (>108 cycles) at an accelerated stress voltage of 3.5 V at 85°C was experimentally observed. The 1 ppm RBER at 2.0 V, 100 ns, and 85°C operation was predicted to be >1018 cycles, based on the dependence of time to breakdown on the stress voltage. This technology matches the requirements of last-level cache and low-power systems on chips for Internet of things applications.

Details

Original languageEnglish
Title of host publication2021 IEEE International Memory Workshop (IMW)
Place of PublicationDresden
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
ISBN (electronic)978-1-7281-8517-0
ISBN (print)978-1-7281-8518-7
Publication statusPublished - May 2021
Peer-reviewedYes

Publication series

SeriesIEEE International Memory Workshop (IMW)
ISSN2330-7978

Workshop

Title13th IEEE International Memory Workshop
Abbreviated titleIMW 2021
Conference number13
Duration16 - 19 May 2021
LocationOnline
CityDresden
CountryGermany

External IDs

ORCID /0000-0003-3814-0378/work/142256177