High-endurance and low-voltage operation of 1T1C FeRAM arrays for nonvolatile memory application

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Jun Okuno - , Sony Group Corporation (Autor:in)
  • Takafumi Kunihiro - , Sony Group Corporation (Autor:in)
  • Kenta Konishi - , Sony Group Corporation (Autor:in)
  • Hideki Maemura - , Sony Group Corporation (Autor:in)
  • Yusuke Shuto - , Sony Group Corporation (Autor:in)
  • Fumitaka Sugaya - , Sony Group Corporation (Autor:in)
  • Monica Materano - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • Tarek Ali - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • Maximilian Lederer - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • Kati Kuehnel - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • Konrad Seidel - , Fraunhofer-Institut für Photonische Mikrosysteme (Autor:in)
  • Uwe Schroeder - , NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • Thomas Mikolajick - , Professur für Nanoelektronik, NaMLab - Nanoelectronic materials laboratory gGmbH (Autor:in)
  • Masanori Tsukamoto - , Sony Group Corporation (Autor:in)
  • Taku Umebayashi - , Sony Group Corporation (Autor:in)

Abstract

A novel 64 kbit one-transistor one-capacitor (1T1C) ferroelectric random access memory (FeRAM) array based on ferroelectric Hf0.5Zr0.5O2 (HZO) was proposed in a prior report. However, this array requires a low operation voltage for integration into advanced technology nodes, and its practical endurance remains unclear. To address these limitations, this study experimentally demonstrates the improved characteristics of a ferroelectric HfO2-based 1T1C FeRAM array. Thickness scaling of the ferroelectric HZO contributes to low-voltage operation of 1T1C FeRAMs, yielding 100% bit functionality at an operation voltage of 2.0 V and operating speed of 16 ns. Furthermore, the endurance performance of the 1T1C FeRAM memory array was investigated for the first time. Excellent cycling endurance (>108 cycles) at an accelerated stress voltage of 3.5 V at 85°C was experimentally observed. The 1 ppm RBER at 2.0 V, 100 ns, and 85°C operation was predicted to be >1018 cycles, based on the dependence of time to breakdown on the stress voltage. This technology matches the requirements of last-level cache and low-power systems on chips for Internet of things applications.

Details

OriginalspracheEnglisch
Titel2021 IEEE International Memory Workshop (IMW)
ErscheinungsortDresden
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers (IEEE)
ISBN (elektronisch)978-1-7281-8517-0
ISBN (Print)978-1-7281-8518-7
PublikationsstatusVeröffentlicht - Mai 2021
Peer-Review-StatusJa

Publikationsreihe

ReiheIEEE International Memory Workshop (IMW)
ISSN2330-7978

Workshop

Titel13th IEEE International Memory Workshop
KurztitelIMW 2021
Veranstaltungsnummer13
Dauer16 - 19 Mai 2021
OrtOnline
StadtDresden
LandDeutschland

Externe IDs

ORCID /0000-0003-3814-0378/work/142256177