Charge trapping memories offer advantages for scaling data flash memories in the sub 50nm groundrule. This paper reviews the progress of the main concepts in charge trapping, NROM and SONOS. Both have undergone significant new developments, like the 4 bits/cell for the NROM and the introduction of new materials for SONOS and new cell structures e.g. including Fin-Fet's. Depending on the progress during the next years these concepts will be even more able to compete with the still dominating floating gate techniques.