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Exploiting transistor-level reconfiguration to optimize combinational circuits

Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review

Contributors

M. Raitza - , Chair of Processor Design (cfaed) (Author)
A. Kumar - , Chair of Processor Design (cfaed) (Author)
M. Völp - , Center for Advancing Electronics Dresden (cfaed) (Author)
D. Walter - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
J. Trommer - , Faculty of Electrical and Computer Engineering (Author)
T. Mikolajick - , Chair of Nanoelectronics (Author)
W.M. Weber - (Author)

Details

Original language	English
Title of host publication	Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017
Publication status	Published - 2017
Peer-reviewed	Yes

External IDs

Scopus	85014200161

Keywords