Experimental proof of the drain-side dielectric breakdown of HKMG nMOSFETs under logic circuit operation
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
Continuous CMOS logic switching results in a consecutive series of gate bias temperature instability and drain (OFF-state) stress. We also show that the asymmetric stress condition leads to a preferential breakdown at the drain side and that neither gate-only nor drain-only stress can reproduce this behavior. The findings are verified by the voltage ratio method as well as dc current-voltage measurements and are caused by trapping and detrapping under the alternating electric field.
Details
Original language | English |
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Article number | 7058394 |
Pages (from-to) | 430-432 |
Number of pages | 3 |
Journal | IEEE electron device letters |
Volume | 36 |
Issue number | 5 |
Publication status | Published - 1 May 2015 |
Peer-reviewed | Yes |
External IDs
ORCID | /0000-0003-3814-0378/work/142256289 |
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Keywords
ASJC Scopus subject areas
Keywords
- ac, BTI, CMOS, HKMG, inverter, off-state, TDDB