Experimental proof of the drain-side dielectric breakdown of HKMG nMOSFETs under logic circuit operation
Publikation: Beitrag in Fachzeitschrift › Forschungsartikel › Beigetragen › Begutachtung
Beitragende
Abstract
Continuous CMOS logic switching results in a consecutive series of gate bias temperature instability and drain (OFF-state) stress. We also show that the asymmetric stress condition leads to a preferential breakdown at the drain side and that neither gate-only nor drain-only stress can reproduce this behavior. The findings are verified by the voltage ratio method as well as dc current-voltage measurements and are caused by trapping and detrapping under the alternating electric field.
Details
Originalsprache | Englisch |
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Aufsatznummer | 7058394 |
Seiten (von - bis) | 430-432 |
Seitenumfang | 3 |
Fachzeitschrift | IEEE electron device letters |
Jahrgang | 36 |
Ausgabenummer | 5 |
Publikationsstatus | Veröffentlicht - 1 Mai 2015 |
Peer-Review-Status | Ja |
Externe IDs
ORCID | /0000-0003-3814-0378/work/142256289 |
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Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- ac, BTI, CMOS, HKMG, inverter, off-state, TDDB