Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

Abstract

Charge sharing poses a fundamental problem in the design of dynamic logic gates, which is nearly as old as digital circuit design itself. Although, many solutions are known, up to now most of them add additional complexity to a given system and require careful optimization of device sizes. Here we propose a simple CMOS-Technology compatible transistor level solution to the charge sharing problem, employing a new class of field effect transistors with multiple independent gates (MIGFETs). Based on mixed-mode simulations in a coordinated device-circuit co-design framework, we show that their underlying device physics provides an inherent suppression of the charge sharing effect. Exemplary circuit layouts as well as discussion on the switching performance are given.

Details

Original languageEnglish
Title of host publication49th European Solid-State Device Research Conference, ESSDERC 2019
PublisherEditions Frontieres
Pages134-137
Number of pages4
ISBN (electronic)9781728115399
Publication statusPublished - Sept 2019
Peer-reviewedYes

Publication series

SeriesEuropean Conference on Solid-State Device Research (ESSDERC)
ISSN1930-8876

Conference

Title49th European Solid-State Device Research Conference
Abbreviated titleESSDERC 2019
Conference number49
Duration23 - 26 September 2019
Degree of recognitionInternational event
LocationUniversity in Kraków
CityCracow
CountryPoland

External IDs

ORCID /0000-0003-3814-0378/work/142256229

Keywords

Keywords

  • charge sharing, domino logic, dynamic logic gates, multi-gate, reconfigurable transistor, Schottky transistors