Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Charge sharing poses a fundamental problem in the design of dynamic logic gates, which is nearly as old as digital circuit design itself. Although, many solutions are known, up to now most of them add additional complexity to a given system and require careful optimization of device sizes. Here we propose a simple CMOS-Technology compatible transistor level solution to the charge sharing problem, employing a new class of field effect transistors with multiple independent gates (MIGFETs). Based on mixed-mode simulations in a coordinated device-circuit co-design framework, we show that their underlying device physics provides an inherent suppression of the charge sharing effect. Exemplary circuit layouts as well as discussion on the switching performance are given.
Details
| Original language | English |
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| Title of host publication | 49th European Solid-State Device Research Conference, ESSDERC 2019 |
| Publisher | Editions Frontieres |
| Pages | 134-137 |
| Number of pages | 4 |
| ISBN (electronic) | 9781728115399 |
| Publication status | Published - Sept 2019 |
| Peer-reviewed | Yes |
Publication series
| Series | European Conference on Solid-State Device Research (ESSDERC) |
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| ISSN | 1930-8876 |
Conference
| Title | 49th European Solid-State Device Research Conference |
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| Abbreviated title | ESSDERC 2019 |
| Conference number | 49 |
| Duration | 23 - 26 September 2019 |
| Degree of recognition | International event |
| Location | University in Kraków |
| City | Cracow |
| Country | Poland |
External IDs
| ORCID | /0000-0003-3814-0378/work/142256229 |
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Keywords
ASJC Scopus subject areas
Keywords
- charge sharing, domino logic, dynamic logic gates, multi-gate, reconfigurable transistor, Schottky transistors