Eliminating Charge Sharing in Clocked Logic Gates on the Device Level Employing Transistors with Multiple Independent Inputs

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Charge sharing poses a fundamental problem in the design of dynamic logic gates, which is nearly as old as digital circuit design itself. Although, many solutions are known, up to now most of them add additional complexity to a given system and require careful optimization of device sizes. Here we propose a simple CMOS-Technology compatible transistor level solution to the charge sharing problem, employing a new class of field effect transistors with multiple independent gates (MIGFETs). Based on mixed-mode simulations in a coordinated device-circuit co-design framework, we show that their underlying device physics provides an inherent suppression of the charge sharing effect. Exemplary circuit layouts as well as discussion on the switching performance are given.

Details

OriginalspracheEnglisch
Titel49th European Solid-State Device Research Conference, ESSDERC 2019
Herausgeber (Verlag)Editions Frontieres
Seiten134-137
Seitenumfang4
ISBN (elektronisch)9781728115399
PublikationsstatusVeröffentlicht - Sept. 2019
Peer-Review-StatusJa

Publikationsreihe

ReiheEuropean Conference on Solid-State Device Research (ESSDERC)
ISSN1930-8876

Konferenz

Titel49th European Solid-State Device Research Conference
KurztitelESSDERC 2019
Veranstaltungsnummer49
Dauer23 - 26 September 2019
BekanntheitsgradInternationale Veranstaltung
OrtUniversity in Kraków
StadtCracow
LandPolen

Externe IDs

ORCID /0000-0003-3814-0378/work/142256229

Schlagworte

Schlagwörter

  • charge sharing, domino logic, dynamic logic gates, multi-gate, reconfigurable transistor, Schottky transistors