Dynamic modeling of hysteresis-free negative capacitance in ferroelectric/dielectric stacks under fast pulsed voltage operation

Research output: Contribution to conferencesPaperContributedpeer-review

Contributors

  • M. Hoffmann - , TUD Dresden University of Technology (Author)
  • Stefan Slesazeck - , TUD Dresden University of Technology (Author)
  • T. Mikolajick - , Chair of Nanoelectronics, TUD Dresden University of Technology (Author)

Abstract

To overcome the fundamental limit of the transistor subthreshold swing of 60 mV/dec at room temperature, the use of negative capacitance (NC) in ferroelectric materials was proposed [1]. Due to the recent discovery of ferroelectricity in CMOS compatible HfO and ZrO based thin films [2], [3], the promise of ultra-low power steep-slope devices seems within reach. However, concerns have been raised about switching-speed limitations and unavoidable hysteresis in NC devices [4], [5]. Nevertheless, it was shown that NC effects without hysteresis can be observed in fast pulsed voltage measurements on ferroelectric/dielectric capacitors [6], which was recently confirmed using ferroelectric Hf0.5Zr0.5O [7], [8]. While in these works only the integrated charge after each pulse was studied, here we investigate for the first time if the transient voltage and charge characteristics are also hysteresis-free.

Details

Original languageEnglish
Pages97-98
Number of pages2
Publication statusPublished - Jun 2019
Peer-reviewedYes

Conference

Title2019 Device Research Conference
Abbreviated titleDRC 2019
Duration23 - 26 June 2019
Degree of recognitionInternational event
LocationUniversity of Michigan, Ann Arbor
CityAnn Arbor
CountryUnited States of America

External IDs

ORCID /0000-0003-3814-0378/work/142256220

Keywords

ASJC Scopus subject areas