Dynamic modeling of hysteresis-free negative capacitance in ferroelectric/dielectric stacks under fast pulsed voltage operation

Publikation: Beitrag zu KonferenzenPaperBeigetragenBegutachtung

Beitragende

  • M. Hoffmann - , Technische Universität Dresden (Autor:in)
  • Stefan Slesazeck - , Technische Universität Dresden (Autor:in)
  • T. Mikolajick - , Professur für Nanoelektronik, Technische Universität Dresden (Autor:in)

Abstract

To overcome the fundamental limit of the transistor subthreshold swing of 60 mV/dec at room temperature, the use of negative capacitance (NC) in ferroelectric materials was proposed [1]. Due to the recent discovery of ferroelectricity in CMOS compatible HfO and ZrO based thin films [2], [3], the promise of ultra-low power steep-slope devices seems within reach. However, concerns have been raised about switching-speed limitations and unavoidable hysteresis in NC devices [4], [5]. Nevertheless, it was shown that NC effects without hysteresis can be observed in fast pulsed voltage measurements on ferroelectric/dielectric capacitors [6], which was recently confirmed using ferroelectric Hf0.5Zr0.5O [7], [8]. While in these works only the integrated charge after each pulse was studied, here we investigate for the first time if the transient voltage and charge characteristics are also hysteresis-free.

Details

OriginalspracheEnglisch
Seiten97-98
Seitenumfang2
PublikationsstatusVeröffentlicht - Juni 2019
Peer-Review-StatusJa

Konferenz

Titel2019 Device Research Conference
KurztitelDRC 2019
Dauer23 - 26 Juni 2019
BekanntheitsgradInternationale Veranstaltung
OrtUniversity of Michigan, Ann Arbor
StadtAnn Arbor
LandUSA/Vereinigte Staaten

Externe IDs

ORCID /0000-0003-3814-0378/work/142256220

Schlagworte

ASJC Scopus Sachgebiete