Conduction barrier offset engineering for DRAM capacitor scaling

Research output: Contribution to journal › Research article › Contributed › peer-review

Contributors

  • Milan Pešić - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • S. Knebel - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • K. Cho - , Samsung (Author)
  • C. Jung - , Samsung (Author)
  • J. Chang - , Samsung (Author)
  • H. Lim - , Samsung (Author)
  • N. Kolomiiets - , KU Leuven (Author)
  • V.V. Afanas'ev - , KU Leuven (Author)
  • T. Mikolajick - , Chair of Nanoelectronics, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • U. Schroeder - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)

Details

Original languageEnglish
Pages (from-to)133-139
Number of pages7
JournalSolid-state electronics
Volume115
Issue numberPart B
Publication statusPublished - 2016
Peer-reviewedYes

External IDs

Scopus 84948085567

Keywords

Library keywords