Backside Thinning and Stress-Relief Techniques for Thin Silicon Wafers

Research output: Contribution to book/Conference proceedings/Anthology/Report › Chapter in book/Anthology/Report › Contributed › peer-review

Contributors

  • Christof Landesberger - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Author)
  • Christoph Paschke - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Author)
  • Hans Peter Spöhrle - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Author)
  • Karlheinz Bock - , Chair of Electronic Packaging Technology, Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Author)

Details

Original languageEnglish
Title of host publication3D Process Technology
PublisherWiley-Blackwell, Berlin
Pages207-226
Number of pages20
Volume3
ISBN (electronic)9783527670109
ISBN (print)9783527334667
Publication statusPublished - 21 Jul 2014
Peer-reviewedYes

External IDs

ORCID /0000-0002-0757-3325/work/139064932

Keywords

ASJC Scopus subject areas

Keywords

  • 3-point bending test, Breaking strength, CMP polishing, Dicing before grinding (DBG), Dicing-by-thinning, Laser dicing, Plasma dicing, Plasma etching, Ring-ball test, Semiconductor devices, Spin etching, Spin-etching, Stress-relief, TAIKO, Thin silicon, Wafer grinding, Wafer thinning