Back-bias reconfigurable field effect transistor: A flexible add-on functionality for 22 nm FDSOI

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

  • V. Sessi - , Global Foundries Dresden (Author)
  • M. Simon - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • Stefan Slesazeck - , TUD Dresden University of Technology (Author)
  • M. Drescher - , Global Foundries Dresden (Author)
  • H. Mulaosmanovic - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • K. Li - , Global Foundries Dresden (Author)
  • R. Binder - , Global Foundries Dresden (Author)
  • S. Waidmann - , Global Foundries Dresden (Author)
  • A. Zeun - , Global Foundries Dresden (Author)
  • A. S. Pawlik - , Global Foundries Dresden (Author)
  • D. Utess - , Global Foundries Dresden (Author)
  • V. Gottleuber - , Global Foundries Dresden (Author)
  • S. Muller - , Global Foundries Dresden (Author)
  • K. Feldner - , Global Foundries Dresden (Author)
  • A. Heinzig - , Chair of Nanoelectronics (Author)
  • S. Dunkel - , Global Foundries Dresden (Author)
  • S. Kolodinski - , Global Foundries Dresden (Author)
  • T. Mikolajick - , Chair of Nanoelectronics, NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • J. Trommer - , NaMLab - Nanoelectronic materials laboratory gGmbH (Author)
  • M. Wiatr - , Global Foundries Dresden (Author)

Abstract

Here we present a highly scalable reconfigurable field effect transistor concept, which is capable of dynamically switching between p-type, n-type, and ambipolar operation modes by adaptively changing the applied back-bias. The devices are processed on full-scale 300 mm wafers and reach gate lengths down to 20 nm, integrable into a 22 nm FDSOI platform with only minor process modifications. We demonstrate symmetric IV characteristics of p- and n-program with Im/loFF ratio up to 103 at a VDD of 0.8 V, and propose an exploitation in hardware security. In arnbipolar mode, frequency multiplication requiring only a single transistor is experimentally demonstrated.

Details

Original languageEnglish
Title of host publication2021 Silicon Nanoelectronics Workshop, SNW 2021
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages2
ISBN (electronic)978-4-86348-781-9
ISBN (print)978-1-6654-0293-4
Publication statusPublished - 2021
Peer-reviewedYes

Publication series

SeriesIEEE Silicon Nanoelectronics Workshop (SNW)

Workshop

Title26th Silicon Nanoelectronics Workshop
Abbreviated titleSNW 2021
Conference number26
Duration13 June 2021
Website
LocationOnline
CountryJapan

External IDs

ORCID /0000-0003-3814-0378/work/142256168