An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~ W/Channel in 65-nm CMOS

Research output: Contribution to journal › Research article › Contributed › peer-review

Contributors

A. T. Do - (Author)
S. M. A. Zeinolabedin - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
D. Jeon - , Chair of Nanoelectronics (Author)
D. Sylvester - (Author)
T. T. Kim - (Author)

Original language	English
Pages (from-to)	126-137
Number of pages	12
Journal	IEEE transactions on very large scale integration (VLSI) systems
Volume	27
Issue number	1
Publication status	Published - 2019
Peer-reviewed	Yes

biomedical electronics, CMOS memory circuits, feature extraction, low-power electronics, medical signal detection, medical signal processing, microprocessor chips, neurophysiology, prosthetics, SRAM chips, leakage consumption, K-means algorithms, SRAM, CMOS process technology, D flip-flop-based memory, ultra-low-voltage 8T static random access memory, dynamic power reduction, time-multiplexed registers, online clustering performance, real-time neural recordings, SSP, area-efficient spike sorting processor, voltage 0.54 V, size 65 nm, frequency 3.2 MHz, Sorting, Iron, Feature extraction, Clustering algorithms, Real-time systems, Memory management, Indexes, Low power, neural recording, real-time recording, spike sorting