An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With $0.175~ W/Channel in 65-nm CMOS

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung

Beitragende

Details

OriginalspracheEnglisch
Seiten (von - bis)126-137
Seitenumfang12
FachzeitschriftIEEE transactions on very large scale integration (VLSI) systems
Jahrgang27
Ausgabenummer1
PublikationsstatusVeröffentlicht - 2019
Peer-Review-StatusJa

Schlagworte

Schlagwörter

  • biomedical electronics, CMOS memory circuits, feature extraction, low-power electronics, medical signal detection, medical signal processing, microprocessor chips, neurophysiology, prosthetics, SRAM chips, leakage consumption, K-means algorithms, SRAM, CMOS process technology, D flip-flop-based memory, ultra-low-voltage 8T static random access memory, dynamic power reduction, time-multiplexed registers, online clustering performance, real-time neural recordings, SSP, area-efficient spike sorting processor, voltage 0.54 V, size 65 nm, frequency 3.2 MHz, Sorting, Iron, Feature extraction, Clustering algorithms, Real-time systems, Memory management, Indexes, Low power, neural recording, real-time recording, spike sorting