This study proposes a novel 1 Mb one-transistor one-capacitor ferroelectric random access memory array based on ferroelectric Hf_0.5Zr_0.5O₂ with 3D cylindrical capacitors. We obtain a perfect functionality with a sufficient memory window at a small projected cylinder area of 0.028 µm² at an operating voltage of 1.8 V by reducing the C_BL and optimizing the structure of the capacitors. We achieve a cycling endurance of 10¹¹ cycles and 1-month retention at 85°C. The reliability is further improved to over 10¹² cycles and 10 years at 85°C retention if the operating voltage is increased to 2.4 V. This technology matches the requirements of last-level cache and low-power systems in chips for Internet of Things applications.