Compact transistor models valid in the bias range of Electro Static Discharge (ESD) puises are needed for optimization of the designed protection circuits. We describe a general electrical breakdown MOSFET model applicable for gate coupled ESD protection optimization and a suitable physically based parameters extraction methodology. The model shows good agreement with the static experimental data. The usability of the model is demonstrated by simulation of a basic protection circuit used in a bidirectional CMOS I/O cell.