For electronic products there are distinct and very high reliability requirements, in particular for applications within aeronautics, medicine and automotive sectors. In order to prove the reliability of integrated circuits packages and their solder joints accelerated aging tests are mandatory (e.g. thermal shock cycles, isothermal storage and vibration stress). Additionally electrical characterization methods are needed and are employing so called daisy chain circuits for the electrical failure detection on solder joints during the experiments while using serial circuits with a permanent monitoring of the impressed current for the to be examined electrical connections of the package. Thus, the described methods for the electrical investigation of the reliability are commonly using dummy packages which include additional internal circuits assembled under laboratory conditions. These methods do not allow the investigation of real integrated circuits. This paper will discuss a new method for electrical characterization of real and soldered high pin count integrated circuits due to the utilization of the included ESD-protective circuit like it is common on wafer level or using advanced boundary scan techniques [1]. This method allows the test of the whole interconnect chain (e.g. PCB connections, bonding connections, interposer connections, soldered connections).