Wafer-scale VLSI implementations of pulse coupled neural networks

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Contributors

Abstract

In this paper, we present a system architecture currently under development that will allow very large (>10^6 neurons, >10^9 synapses) reconfigurable networks to be built, in the form of interlinked dies on a single wafer. Reconfigurable routing and complex adaptation/plasticity across several timescales in neurons and synapses allow for the implementation of large-scale biologically realistic neuronal networks and behaviors. Compared to biology the network dynamics will be about 104 to 105 times faster, so that developmental plasticity can be studied in detail.

Details

Original languageEnglish
Title of host publication4th Multi-Conference on Systems, Signals & Devices (SSD'07)
Pages409
Number of pages1
Publication statusPublished - 1 Mar 2007
Peer-reviewedYes

Publication series

SeriesIEEE SSD International Multi-Conference on Systems, Signals and Devices
ISSN2474-0438