Wafer-scale VLSI implementations of pulse coupled neural networks
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
In this paper, we present a system architecture currently under development that will allow very large (>10^6 neurons, >10^9 synapses) reconfigurable networks to be built, in the form of interlinked dies on a single wafer. Reconfigurable routing and complex adaptation/plasticity across several timescales in neurons and synapses allow for the implementation of large-scale biologically realistic neuronal networks and behaviors. Compared to biology the network dynamics will be about 104 to 105 times faster, so that developmental plasticity can be studied in detail.
Details
Original language | English |
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Title of host publication | 4th Multi-Conference on Systems, Signals & Devices (SSD'07) |
Pages | 409 |
Number of pages | 1 |
Publication status | Published - 1 Mar 2007 |
Peer-reviewed | Yes |
Publication series
Series | IEEE SSD International Multi-Conference on Systems, Signals and Devices |
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ISSN | 2474-0438 |