Wafer-scale VLSI implementations of pulse coupled neural networks
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
In this paper, we present a system architecture currently under development that will allow very large (>10^6 neurons, >10^9 synapses) reconfigurable networks to be built, in the form of interlinked dies on a single wafer. Reconfigurable routing and complex adaptation/plasticity across several timescales in neurons and synapses allow for the implementation of large-scale biologically realistic neuronal networks and behaviors. Compared to biology the network dynamics will be about 104 to 105 times faster, so that developmental plasticity can be studied in detail.
Details
Originalsprache | Englisch |
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Titel | 4th Multi-Conference on Systems, Signals & Devices (SSD'07) |
Seiten | 409 |
Seitenumfang | 1 |
Publikationsstatus | Veröffentlicht - 1 März 2007 |
Peer-Review-Status | Ja |
Publikationsreihe
Reihe | IEEE SSD International Multi-Conference on Systems, Signals and Devices |
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ISSN | 2474-0438 |