Virtualization of Hardware Accelerators in a Network-on-Chip
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Networks-on-Chip (NoCs) are beneficial for reconfigurable systems that require a high degree of parallel and scalable communication. NoCs are reusable as hardware accelerators can be exchanged via dynamic partial reconfiguration. Nevertheless, NoCs are not conceptualized for the use in a virtualized environment where applications from multiple virtual machines have to share reconfigurable resources. Many state-of-the-art works assign hardware accelerators exclusively to a single virtual machine, which limits the number of processed hardware tasks and leads to underutilization of FPGA area. Therefore, we provide a NoC virtualization layer that allows the execution of several pipelined
hardware tasks agnostic of the location of the required hardware accelerators. The allocation of tasks to processing elements can be adapted to dynamically changing requirements, while unauthorized access is prohibited. Further, we provide a scheduler that schedules hardware tasks in spatial and temporal respect to processing elements in the NoC. The proposed heuristic considers task priorities, a possible reuse of accelerators and hop counts. In overload conditions, the tasks with the lowest priorities are postponed. Our virtualization layer increases the number of tasks processed by 22.6% compared to an approach that grants exclusive access.
hardware tasks agnostic of the location of the required hardware accelerators. The allocation of tasks to processing elements can be adapted to dynamically changing requirements, while unauthorized access is prohibited. Further, we provide a scheduler that schedules hardware tasks in spatial and temporal respect to processing elements in the NoC. The proposed heuristic considers task priorities, a possible reuse of accelerators and hop counts. In overload conditions, the tasks with the lowest priorities are postponed. Our virtualization layer increases the number of tasks processed by 22.6% compared to an approach that grants exclusive access.
Details
Original language | English |
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Title of host publication | Proceedings - 2023 26th Euromicro Conference on Digital System Design, DSD 2023 |
Editors | Smail Niar, Hamza Ouarnoughi, Amund Skavhaug |
Pages | 726 - 733 |
Number of pages | 8 |
ISBN (electronic) | 9798350344196 |
Publication status | Published - 8 Sept 2023 |
Peer-reviewed | Yes |
External IDs
ORCID | /0000-0003-2571-8441/work/143495885 |
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ORCID | /0000-0002-8604-0139/work/143496899 |
Scopus | 85189180937 |
Mendeley | 4f7ee3c6-1581-3cc3-9118-02058528b6b3 |
Keywords
Research priority areas of TU Dresden
DFG Classification of Subject Areas according to Review Boards
Subject groups, research areas, subject areas according to Destatis
ASJC Scopus subject areas
Keywords
- FPGA virtualization, Network-on-chip, hypervisor, hypervisor for re-configurable computing, Network-on-chip, virtualization