Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous Embedded Systems.
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Continued transistor scaling and increasing power density have led to considerable increase in fault-rates in silicon nanotechnology-based real-Time systems. Cross-layer fault tolerance techniques present a more cost-efficient methodology for adapting to such increased fault rates by distributing fault-Tolerance to different layers. To this end, we propose a methodology for integrating the design space exploration (DSE) for taskmapping on heterogeneous hardware-platforms with designing cross-layer reliability. Specifically, we model the DSE for task-mapping with cross-layer reliability as a tree search problem and use Monte Carlo Tree Search for task-mapping and scheduling applications with specific reliability requirements. The proposed methodology results in considerable improvements over a standalone approach to task-mapping and implementing cross-layer reliability.
Details
Original language | English |
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Title of host publication | VLSI-SoC |
Pages | 1-6 |
Number of pages | 6 |
ISBN (electronic) | 9781665426145 |
Publication status | Published - 2021 |
Peer-reviewed | Yes |
External IDs
Scopus | 85117702954 |
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