Continued transistor scaling and increasing power density have led to considerable increase in fault-rates in silicon nanotechnology-based real-Time systems. Cross-layer fault tolerance techniques present a more cost-efficient methodology for adapting to such increased fault rates by distributing fault-Tolerance to different layers. To this end, we propose a methodology for integrating the design space exploration (DSE) for taskmapping on heterogeneous hardware-platforms with designing cross-layer reliability. Specifically, we model the DSE for task-mapping with cross-layer reliability as a tree search problem and use Monte Carlo Tree Search for task-mapping and scheduling applications with specific reliability requirements. The proposed methodology results in considerable improvements over a standalone approach to task-mapping and implementing cross-layer reliability.