User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects

Research output: Contribution to journal › Research article › Contributed › peer-review

Contributors

  • Koichi Ishida - , Chair of Circuit Design and Network Theory, The University of Tokyo, Tokyo University of Agriculture (Author)
  • Naoki Masunaga - , Tokyo University of Agriculture (Author)
  • Ryo Takahashi - , Tokyo University of Agriculture (Author)
  • Tsuyoshi Sekitani - , Tokyo University of Agriculture (Author)
  • Shigeki Shino - , Mitsubishi Seishi Kabushiki Kaisha (Author)
  • Ute Zschieschang - , Max Planck Institute for Solid State Research (Author)
  • Hagen Klauk - , Max Planck Institute for Solid State Research (Author)
  • Makoto Takamiya - , Tokyo University of Agriculture (Author)
  • Takao Someya - , Tokyo University of Agriculture (Author)
  • Takayasu Sakurai - , Tokyo University of Agriculture (Author)

Abstract

In this paper we present User Customizable Logic Paper (UCLP) with a Sea-of Transmission-Gates (SOTG) of 2-V organic CMOS transistors. This can enable users to fabricate custom integrated circuits, by printing 200 wide interconnects with at-home ink-jet printers for the prototyping of large-area electronics and educational purposes. The SOTG reduces the area of the circuits in UCLP by between 11% and 85% compared with a conventional gate array architecture.

Details

Original languageEnglish
Article number5599941
Pages (from-to)285-292
Number of pages8
JournalIEEE journal of solid-state circuits
Volume46
Issue number1
Publication statusPublished - 1 Jan 2011
Peer-reviewedYes

External IDs

Scopus 78650902687
ORCID /0000-0002-4152-1203/work/165453403

Keywords

Keywords

  • Computer architecture, Microprocessors, Integrated circuit interconnections, Transistors, Ink jet printing, Logic gates, Resistance