User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects

Publikation: Beitrag in Fachzeitschrift › Forschungsartikel › Beigetragen › Begutachtung

Beitragende

  • Koichi Ishida - , Professur für Schaltungstechnik und Netzwerktheorie, The University of Tokyo, Tokyo University of Agriculture (Autor:in)
  • Naoki Masunaga - , Tokyo University of Agriculture (Autor:in)
  • Ryo Takahashi - , Tokyo University of Agriculture (Autor:in)
  • Tsuyoshi Sekitani - , Tokyo University of Agriculture (Autor:in)
  • Shigeki Shino - , Mitsubishi Seishi Kabushiki Kaisha (Autor:in)
  • Ute Zschieschang - , Max-Planck-Institut für Festkörperforschung (Autor:in)
  • Hagen Klauk - , Max-Planck-Institut für Festkörperforschung (Autor:in)
  • Makoto Takamiya - , Tokyo University of Agriculture (Autor:in)
  • Takao Someya - , Tokyo University of Agriculture (Autor:in)
  • Takayasu Sakurai - , Tokyo University of Agriculture (Autor:in)

Abstract

In this paper we present User Customizable Logic Paper (UCLP) with a Sea-of Transmission-Gates (SOTG) of 2-V organic CMOS transistors. This can enable users to fabricate custom integrated circuits, by printing 200 wide interconnects with at-home ink-jet printers for the prototyping of large-area electronics and educational purposes. The SOTG reduces the area of the circuits in UCLP by between 11% and 85% compared with a conventional gate array architecture.

Details

OriginalspracheEnglisch
Aufsatznummer5599941
Seiten (von - bis)285-292
Seitenumfang8
FachzeitschriftIEEE journal of solid-state circuits
Jahrgang46
Ausgabenummer1
PublikationsstatusVeröffentlicht - 1 Jan. 2011
Peer-Review-StatusJa

Externe IDs

Scopus 78650902687
ORCID /0000-0002-4152-1203/work/165453403

Schlagworte

Schlagwörter

  • Computer architecture, Microprocessors, Integrated circuit interconnections, Transistors, Ink jet printing, Logic gates, Resistance