User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
With recent advances in printable large-area electronics [1, 2], it is not a fantasy anymore to print macroscopic-level organic ICs by ink-jet printers. To prototype the organic circuits for the higher integration level, we propose User Customizable Logic Paper (UCLP). The UCLP can be easily customized by the user and operated in a speed for educational purposes that one can see how the circuit operates with one's naked eyes. With an ordinary ink-jet printer, one can utilize UCLP to make one's own circuit by printing customized interconnects on the prefabricated array of organic transistors. This paper demonstrates the feasibility and in-field customizability of UCLP with Sea-of Transmission-Gates (SOTG) of organic CMOS transistors. This type of technology will provide ways to add programmability for ICs used in large-area electronics such as smart flexible displays, power transmission sheets, and electronic skin for robots.
Details
| Original language | English |
|---|---|
| Title of host publication | 2010 IEEE International Solid-State Circuits Conference - (ISSCC) |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Pages | 138-139 |
| Number of pages | 2 |
| ISBN (print) | 978-1-4244-6035-9 |
| Publication status | Published - 11 Feb 2010 |
| Peer-reviewed | Yes |
Conference
| Title | 2010 IEEE International Solid-State Circuits Conference - (ISSCC) |
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| Duration | 7 - 11 February 2010 |
| Location | San Francisco, CA, USA |
External IDs
| Scopus | 77952162686 |
|---|---|
| ORCID | /0000-0002-4152-1203/work/165453400 |
Keywords
Keywords
- Ink jet printing, Integrated circuit interconnections, Multiplexing, Variable structure systems, Semiconductor device measurement, Logic functions, Light emitting diodes, Logic gates, Propagation delay, Electrical resistance measurement