Towards Large-Scale Top-Down Microarchitecture Analysis Using the Score-P Framework

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Abstract

The Top-Down Microarchitecture Analysis Method introduced by Yasin [31] established a simple yet effective generic approach to performance analysis. It can be used to analyze whichmicro architectural resource poses a bottleneck during the execution of arbitrary codes. The recently introduced Golden Cove microarchitecture used in Intel’s Sapphire Rapids processors provides an extended, automated hardware support for this analysis. In this paper, we describe the implementation of this micro architectural feature, integrate support into the performance measurement infrastructure Score-P, and explore the capabilities of the resulting tool with two example applications: The Computational Fluid Dynamics (CFD) solver for turbo-machinery applications Hydra [23], and the open-source weather and climate model ICON [32].

Details

Original languageEnglish
Title of host publicationEuro-Par 2024: Parallel Processing Workshops
EditorsSilvina Caino-Lores, Demetris Zeinalipour, Thaleia Dimitra Doudali, David E. Singh, Gracia Ester Martín Garzón, Leonel Sousa, Diego Andrade, Tommaso Cucinotta, Donato D'Ambrosio, Patrick Diehl, Manuel F. Dolz, Admela Jukan, Raffaele Montella, Matteo Nardelli, Marta Garcia-Gasulla, Sarah Neuwirth
PublisherSpringer Science and Business Media B.V.
Pages189-200
Number of pages12
ISBN (electronic)978-3-031-90200-0
ISBN (print)978-3-031-90199-7
Publication statusPublished - 2025
Peer-reviewedYes

Publication series

SeriesLecture notes in computer science
Volume15385 LNCS
ISSN0302-9743

Conference

Title30th International European Conference on Parallel and Distributed Computing
Abbreviated titleEuro-Par 2024
Conference number30
Duration26 - 30 August 2024
Website
LocationUniversity Carlos III of Madrid
CityMadrid
CountrySpain

External IDs

ORCID /0000-0001-9601-8683/work/188000050

Keywords

Sustainable Development Goals